This invention relates generally to semiconductor devices and systems and specifically to a pipelined analog-to-digital converter.
Analog-to-digital conversion is the process of converting an analog signal, which is most commonly represented as voltage, into a digital format. Determining a digital value which represents a particular analog input is known as xe2x80x9cquantization.xe2x80x9d Serial, delta-sigma or oversampling, parallel, and pipelined are some of the many different analog-to-digital conversion architectures which exist. Different architectures are suited to different needs.
The serial analog-to-digital architecture offers a wide range of performance in analog-to-digital conversion, from low power and low resolution to quantizations with very high resolutions. A serial architecture typically quantizes analog data at the rate of one bit per cycle. Therefore, a digital sample having N bits of resolution will take N cycles to fully quantize.
Delta-sigma analog-to-digital architecture is often used in audio signal processing. The architecture is designed to translate high-speed, low-resolution samples into higher-resolution, lower-speed output. This process is also referred to as oversampling because more samples of the analog data are quantized than actually become output.
By contrast, parallel analog-to-digital architecture provides the fastest quantization rate per analog signal. In the parallel (or xe2x80x9cflashxe2x80x9d) architecture, a digital value per cycle is produced for each analog data sample, without regard to N, the number of bits of resolution. Parallel architecture requires that all quantization levels be simultaneously compared to the analog signal. This results in the use of 2Nxe2x88x921 comparators and 2N+1 resistors to achieve a digital value, with N bits of resolution, per cycle.
Pipelined analog-to-digital architecture, like serial analog-to-digital architecture, is a method of quantizing an analog signal in stages. Algorithms exist for obtaining either 1 or 1.5 bits of resolution per stage. In a 1.5-bit per stage converter, the digital output of each stage is either 1, 0, or xe2x88x921. In a 1-bit per stage converter, the digital output of each stage is either 1 or xe2x88x921 (or 1 or 0). For either algorithm, N stages are used for an N-bit digital value. One bit is resolved at each stage with the result and analog signal sample passed along to the next stage for resolution of another bit.
In a 1.5 bit per stage converter, the other xc2xd bit in each stage is redundant. Digital correction logic eliminates the redundancy to produce an N-bit result. Producing a single digital value for a single analog input requires N cycles, one for each stage. However, the pipelining permits a high degree of parallelism, so that one output per cycle can be produced after the pipeline fills up.
Related co-pending patent application 09/371,416 discloses a pipelined analog-to-digital converter with relaxed inter-stage amplifier requirements. In one aspect, the present invention provides a number of implementations of a circuit that meets the criteria of the co-pending application.
For example, in one embodiment a pipelined analog-to-digital converter includes a first stage of an analog-to-digital converter having a first resolution. The first stage includes a three capacitor switched capacitor circuit. The analog-to-digital converter further includes one or more subsequent analog-to-digital converter stages. Each of the subsequent stages has a second resolution which is coarser than the first resolution. The first and subsequent stages are pipelined together to provide a digital output signal.
In another embodiment, an analog-to-digital converter includes multiple stages. The first stages includes at least three comparators. A decoder is coupled to each of the comparators and provides an output that is related to the magnitude of an analog input signal. A switched capacitor circuit receives the analog input signal and a variable reference voltage, the magnitude of which is selected by the decoder. The switched capacitor circuit also provides a residue signal. A second stage has an input coupled to the switched capacitor circuit output of the first stage. This second includes a sub-analog-to-digital converter that is configured to quantize the residue signal. Third and subsequent stages may also be included.
One advantage of certain embodiments of the present invention is the reduction of the signal swing of inter-stage amplifiers by a factor of two. Such a reduction can be significant when low power supply voltages limit the output range of an operational amplifier. Another advantage of certain of these embodiments is the simplification of the sub-digital-to-analog operation by reducing the required range of the reference voltage VREF and reducing the number of components that must accurately match in order to generate required fractions of VREF.